A flash memory is typically configured by an array of multiplicity of memory cells aligned in the word line direction and the bit line direction. A memory cell is configured by a stacked gate structure in which a floating gate electrode, interelectrode insulating film, and control gate electrode are stacked in the listed sequence. As flash memory increases its storage capacity through densification, features within the memory cell are packed in tighter dimensions. Dimensions typically affected by the densification are widths of floating gate electrodes and element isolation trenches.
The interelectrode insulating film is often configured by an ONO structure in which a silicon nitride film is interposed between a top silicon oxide film and a bottom silicon oxide film. The silicon nitride film in the middle layer of the stack traps electrons that positively affect the programming properties of the cell. As the element isolation trenches become narrower, the electrons trapped in the silicon nitride film of the interelectrode insulating film located above the element isolation insulating film cause a shift in the programming threshold of the adjacent cell, which typically causes programming errors. Further, in attempt to improve the coupling ratio, the control gate electrode is typically formed extensively to almost reach the foot of each floating gate electrode so as to nearly fill the word line direction gaps between the floating gate electrodes. As a result, the control gate electrode is placed in close proximity with the element isolation insulating film. An erase operation performed under such configuration caused flow of leakage current between the control gate electrode and the silicon substrate located in the region corresponding to the element isolation insulating film, thereby degrading the erase properties of the memory cells.